“Going from a 3-gear bicycle to a 20-gear bicycle” — Scientists inch closer to new tech that combines ultra expensive but super fast SRAM and DRAM

• Stanford scientists are looking to combine SRAM and DRAM
• The new memory type would help solve issues with AI computing
• Gain Cell memory looks to bridge the gap between the two types

The development of more energy-efficient hardware for artificial intelligence (AI) systems is receiving increased support, with a focus on improving memory technology.

A hybrid type of memory that blends the high density of DRAM (Dynamic Random-Access Memory) with the speed of SRAM (Static Random-Access Memory) is at the forefront of this effort.

The project is being led by electrical engineers at Stanford University, with the team’s goal being to create faster, more efficient memory hardware for AI applications that addresses the current limitations in processing power and energy consumption.

Memory, a key AI bottleneck – hybrid gain cell memory to the rescue

This research is being funded under the CHIPS and Science Act, with a recent boost of $16.3 million in US Department of Defense funding to the California-Pacific-Northwest AI Hardware Hub.

AI systems are heavily reliant on hardware that can efficiently move and process large volumes of data. However, moving data between memory and logic unites takes time, which slows down GPUs and leads to increased energy consumption.

As AI models become larger and more complex, these memory bottlenecks become more pronounced. Therefore, faster and denser memory located directly on chips is seen as a potential solution to this problem.

Stanford University’s H.-S. Philip Wong, an electrical engineer and chair of the AI Hardware Hub, emphasizes the importance of memory in making AI hardware more energy efficient.

Wong’s team has turned to a new type of memory design called Gain Cell memory, which combines the advantages of both DRAM and SRAM. The hybrid gain cell offers a middle ground which has the small footprint of DRAM, but it also provides the faster readout speeds characteristic of SRAM.

The key difference in this new design is the use of two transistors—one for writing data and one for reading rather than the capacitor found in…